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Description:
Code Checks
Syntax
The syntax is checked to see if it conforms to the VHDL standard
Level: Error
Type check
The code is type checked. This catches all type errors and missing identifiers.
Level: Error
Signals declared but not assigned
For each architecture, this rule finds signals declared in the declaration section (i.e. before "begin") that are never assigned a value.
Level: Warning
Signals declared but not read
For each architecture, this rule finds signals declared but never read.
Level: Warning
Signals read but not assigned
For each architecture, this rule finds signals which are read but never assigned a value.
Level: Critical warning
Sensitivity list
For each process, this rule checks that every signal that is read in a combinational section of the process is in the sensitivity list. Combinational sections are defined as any code block not within an if(rising_edge(clk)), or similar edge triggering condition.
Level: Warning
Latches
For each process, this rule checks that if a signal is assigned down one combinational branch of a process (see above) it is assigned down all.
Level: Warning
Port not read
Check that each input port is read
Level: Warning
Port not written
Check that each output port is written
Level: Warning
Duplicate library import
Check that each imported library is only imported once
Level: Warning
Duplicate package import
Check that each imported package is only imported once
Level: Warning
Deprecated packages
Check that deprecated packages such as std_logic_arith are not imported
Level: Warning
Instantiation checks
For each procedure, entity or component instantiation, this rule checks:
- that all of the ports of the component are connected
- if you have tried to assign, by name, ports that do not exist in the component being instantiated
- if you have tried to assign more ports than the component has (if using positional association)
Level: Warning