Do these results look wrong? Let us know so we can fix it.
The syntax is checked to see if it conforms to the VHDL standard
The code is type checked. This catches all type errors and missing identifiers.
Signals declared but not assigned
For each architecture, this rule finds signals declared in the declaration section (i.e. before "begin") that are never assigned a value.
Signals declared but not read
For each architecture, this rule finds signals declared but never read.
Signals read but not assigned
For each architecture, this rule finds signals which are read but never assigned a value.
Level: Critical warning
For each process, this rule checks that every signal that is read in a combinational section of the process is in the sensitivity list. Combinational sections are defined as any code block not within an if(rising_edge(clk)), or similar edge triggering condition.
For each process, this rule checks that if a signal is assigned down one combinational branch of a process (see above) it is assigned down all.
Port not read
Check that each input port is read
Port not written
Check that each output port is written
Duplicate library import
Check that each imported library is only imported once
Duplicate package import
Check that each imported package is only imported once
Check that deprecated packages such as std_logic_arith are not imported
For each procedure, entity or component instantiation, this rule checks:
- that all of the ports of the component are connected
- if you have tried to assign, by name, ports that do not exist in the component being instantiated
- if you have tried to assign more ports than the component has (if using positional association)